A current common requirement for an electronic circuit and particularly for electronic circuits manufactured as integrated circuits in semiconductor processes is an on-board or embedded array of memory storage elements. These elements may be provided as dynamic random access memory (DRAM) cells and alternatively as static random access memory cells (SRAM) cells. DRAM and SRAM memories are described as “volatile” memory cells, in that if the power to the integrated circuit device is removed, the stored data will be lost. DRAM cells may be provided in very dense arrays, since a DRAM cell requires only a single access transistor and a storage capacitor; however, DRAM circuits have relatively slow access time for reads and writes, and require somewhat complicated control circuitry, and each DRAM cell stores data as charge on a leaky capacitor, so that the DRAM array must be refreshed periodically to maintain state. This requires either that processors periodically stop other operations and perform the refresh cycles, or that a dedicated memory controller (more often used in recently produced devices) perform the refresh cycles. SRAM arrays require more silicon area, since each bit cell is a latch formed of typically six transistors (6T) or more; however, the SRAM cells will retain data so long as a supply voltage is present. Further advantages are that access times are very fast compared to DRAM cells, making SRAM cells particularly attractive as scratchpad or working data storage, such as cache memory for processor. Recent system on a chip (SOC) designs often incorporate one or more “cores”. These cores are often predesigned popular processors such as DSPs, ARMs, RISC or microprocessors, arranged with a level one (L1) cache memory of SRAM cells laid out near or adjacent to the processor to make very fast processing operations possible.
Increasingly, integrated circuits are used to implement functions in battery operated devices. For example, SOCs may be used to provide all or most of the circuitry needed to implement the main functions of a cellphone, laptop computer, netbook computer, audio or video player, camcorder or camera, smartphone or PDA. In these devices, customer defined logic or licensed processor core designs may be integrated with other predefined or macro cells such as microprocessors, digital signal processors, cores such as ARM, RISC or similar core functions, cell phone modules, and the like.
In an SRAM bit cell, data is stored on two storage nodes which are inversely related. A pair of CMOS inverters, formed of four MOS transistors, is arranged as a latch cell, each storage node being formed of the gate terminals of two MOS transistors and receiving the output of an inverter formed of two MOS transistors in complementary MOS (CMOS) technology.
FIG. 1 depicts a typical SRAM bit cell 10 in a 6T arrangement. In FIG. 1, a pair of MOS pass gates PG1 and PG2 couple a pair of data lines referred to as “bit lines” BL and BLB to storage nodes SN1 and SN2, respectively. The pass gate transistors PG1 and PG2 are typically formed of NMOS transistors as is known in the art. A positive supply voltage Vdd, which may be from 0.6 Volts to 3.0 or more volts, depending on the technology, is shown. Pull up transistors PU1 and PU2 are formed of PMOS transistors and couple the positive supply to one or the other storage nodes, depending on the state of the SRAM cell 10. A second supply voltage Vss, usually placed at ground, is shown.
Two pull down transistors PD1 and PD2, which are also NMOS transistors, couple this negative or ground voltage Vss to one or the other storage node labeled SN1 and SN2, depending on the state of the bit cell. The bit cell is a latch that will retain its data state indefinitely so long as the supplied power is sufficient to operate the circuit correctly. Two CMOS inverters formed of PU1, PD1 and PU2, PD2 are “cross coupled” and they operate to reinforce the stored charge on the storage nodes SN1 and SN2 continuously. The two storage nodes are inverted one from the other, as shown in the figure. When SN1 is a logical “1”, usually a high voltage, SN2 is at the same time a logical “0”, usually a low voltage, and vice versa.
When SRAM bit cell 10 is written to, complementary write data signals are placed on the bit line pair BL and BLB. A positive control signal on a wordline WL is coupled to the gate of both pass gates PG1 and PG2. The transistors PU1, PD1 and PU2, PD2 are sized such that the data on the bit lines may overwrite the stored data and thus write the SRAM bit cell 10.
When the SRAM bit cell 10 is read from, a positive voltage is placed on the word line WL, and the pass gates PG1 and PG2 allow the bit lines BL and BLB to be coupled to, and receive the data from, the storage nodes SN1 and SN2. Unlike a dynamic memory cell, the SRAM bit cell does not lose its stored state during a read if the power supply Vdd is maintained at a sufficiently high level, so no “write back” operation is required after a read.
The bit lines BL and BLB form a complementary pair of data lines. As is known to those skilled in the art, these paired data lines may be coupled to a differential sense amplifier (not shown); the differential voltage can be sensed and amplified, as is known in the art. This amplified sensed output signal may then be output as data to other logic circuitry in the device.
FIG. 2 depicts another form of a conventional SRAM bit cell 12 that uses 8 transistors (8T) and has an additional functionality in the form of a read port 14. In FIG. 2, the 6T cell 10 such as is shown in FIG. 1 is used. SRAM bit cell 12 additionally has a read port 14 of two NMOS transistors, read port pull down transistor RPD and read port pass gate transistor RPG. A read word line (RWL) is provided that is dedicated to “reads” only. The previous word line WL in FIG. 1 now becomes a write only word line WWL in the 8T cell 12 of FIG. 2. Advantages of a separate read port are that the possibility of “read disturbs” is reduced, because the data stored in the bit cell affected by the read operations; instead, the read pull down transistor RPD is either on or off based on the storage node SN2 voltage that is coupled to the gate terminal of the transistor RPD. Because an NMOS transistor has gain, the stored data signal at SN2 is amplified by the gain of transistor RPD; and when the read word line RWL has a positive voltage placed on it, read pass gate transistor RPG turns on and couples the read bit line RBL to the read pull down transistor RPD, and the read port therefore outputs a corresponding data bit on the read bit line RBL. In many applications, SRAM arrays of many bit cells are used that store data or programs for retrieval and use later. The SRAM cells may experience many more read operations than write operations in the same time period. Thus, it is very advantageous to have the read operations isolated from the bit cell by the read port circuit 14. This is true even though the 8T cell uses slightly more layout area in silicon to implement it. Further, when attempting to save power, the Vcc,min characteristic measurement becomes much more critical for the read circuitry, as that is the portion of the circuitry that is active most often.
FIG. 3 depicts another known SRAM bit cell 20 arrangement that uses ten transistors (10T). In this form, the circuit has two read ports, one coupled to each storage node SN1 and SN2 of the 6T cell 10. Each read port 22 and 24 has a separate control line (RWL1 and RWL2) and a separate pull down NMOS transistor and pass gate NMOS transistor. The two read bit lines RBL1 and RBL2 are coupled by the pass gate transistors RPG1, RPG2 to the pull down transistors RPD1 and RPD2 respectively. The pull down transistors each have a gate terminal coupled a respective storage node SN1 and SN2. The read operations may be performed independently or simultaneously. The use of the two read ports provides additional flexibility and allows two outputs to be read from the cell simultaneously.
The continuing and increasing demand for low power integrated circuits, particularly for more complicated battery powered, portable devices, requires that SRAM cells have good power consumption characteristics. One measure of the power consumption is the standby leakage current (hereinafter, “Isb”). When the SRAM cell is not being used, the SRAM array may be placed in a standby mode. The leakage current consumed during standby, Isb, should be minimized. Further, it is known in the art to reduce power consumed in CMOS circuitry during standby mode by reducing the positive power supply as far as possible while operating reliably. The metric used to determine this Vcc potential is referred to as “Vcc,min.”. It is clearly advantageous to provide SRAM cells with a low Vcc,min value. This is difficult to do reliably for the 6T storage cells, however, due to process variations and other constraints increasingly imposed by shrinking device sizes and process advances.
However, the circuits must also have excellent access time (read speed) and operate reliably without “read disturb” errors. This last characteristic may be described as the stability of the circuit. One method for maintaining stability is to decrease the Vcc,min to the SRAM storage cells. Further, as semiconductor processes continue to advance, device sizes continue to shrink. The use of smaller and smaller devices results in devices with increasingly broad performance variation. In order to maintain reliable operation with such devices, a lower Vcc,min is required. While lowering Vcc,min is a good approach to lower power consumption, lowering Vcc,min in the SRAM array is also desirable.
Thus, there is a continuing need for an improved SRAM bit cell structure that has a lower standby leakage current Isb, improved Vcc,min for lower standby power, and improved access speed particularly during read operations, while remaining compatible with state of the art semiconductor processes for fabricating integrated circuits, without adding significant steps or significant added costs.